1. Technical Field
Example embodiments of the present disclosure relate to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a dual polysilicon gate and methods of a semiconductor device using the same.
2. Related Art
Recently, complementary metal-oxide-semiconductor (CMOS) circuits have been widely used to reduce power consumption of semiconductor devices. CMOS circuits typically include N-channel MOS (NMOS) transistors and P-channel MOS (PMOS) transistors which are disposed in and/or on the same substrate. In general, PMOS transistors may have a buried channel structure. As CMOS circuits become more highly integrated, channel lengths of the PMOS transistors have been gradually reduced. In the event that the PMOS transistors have a buried channel structure, the PMOS transistors may suffer greatly from a short channel effect which leads to a channel leakage current. Thus, a dual polysilicon gate structure has been proposed to realize a PMOS transistor having a surface channel structure. The dual polysilicon gate structure may include an N-type polysilicon pattern doped with N-type impurities and a P-type polysilicon pattern doped with P-type impurities. The P-type polysilicon pattern may be used as a gate of the PMOS transistor, and the N-type polysilicon pattern may be used as a gate of the NMOS transistor.
To form the dual polysilicon gate structure, a gate insulation layer may be formed on a substrate having an NMOS transistor region and a PMOS transistor region, and a polysilicon layer may be formed on the gate insulation layer. The polysilicon layer may be doped with impurities of a first conductivity type, for example, N-type impurities during or after formation of the polysilicon layer. A mask pattern may be then formed to expose the PMOS transistor region and to cover the NMOS transistor region, and impurities of a second conductivity type may be injected into the polysilicon layer of the first conductivity type in the PMOS transistor region using the mask pattern as an implantation mask. Thus, the polysilicon layer of the first conductivity type in the PMOS transistor region may be converted into a polysilicon layer of a second conductivity type, for example, a P-type polysilicon layer. If an impurity concentration of the N-type polysilicon layer is too high, it may be difficult to convert the N-type polysilicon layer in the PMOS transistor region into a P-type polysilicon layer using the counter doping process. In contrast, if the impurity concentration of the N-type polysilicon layer is too low, the N-type polysilicon layer in the PMOS transistor region may be more readily converted into a P-type polysilicon layer using the counter doping process. When the impurity concentration of the N-type polysilicon layer is too low, however, electrical characteristics of the N-type polysilicon layer in the NMOS transistor region may be degraded.
To solve the above disadvantages, an intrinsic polysilicon layer may be formed on a substrate having an NMOS transistor region and a PMOS transistor region. Subsequently, N-type impurities may be selectively injected into the intrinsic polysilicon layer in the NMOS transistor region, and P-type impurities may be selectively injected into the intrinsic polysilicon layer in the PMOS transistor region. However, in this case, two different mask patterns, for example, first and second mask patterns may be required to form the dual polysilicon gate structure. The first mask pattern may be formed to selectively expose the NMOS transistor region using a first photo mask, and the second mask pattern may be formed to selectively expose the PMOS transistor region using a second photo mask. That is, two separate photo masks may be required which may lead to an increase in fabrication costs of the CMOS circuits. Further, additional processes, for example, first and second photoresist strip processes for removing the first and second mask patterns may be required. Moreover, first and second cleaning processes for removing residues of the first and second mask patterns may also be required. Consequently, the number of total process steps may be increased.